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Of these, the rst three segments form a simple open curve, each point of which can be reached by the arm endpoint. The fact that the fourth segment cannot be reached by the arm endpoint poses no algorithmic problems since the endpoints of the said simple open curve in Figure 5.23, points 1 and 7 can easily be recognized from the fact that they always lie on the W -space boundary and hence correspond to the maximum value of the joint value l2 . This fact will help in showing the algorithm convergence. An important statement that helps simplify the path planning procedure of the PP arm follows directly from Figure 5.23: Lemma 5.4.1. For the Cartesian two-link arm, if the target point T is reachable from the starting point S, then there exists a path from S to T such that it corresponds to a monotonic change of the joint value l1 .

S T This can be shown as follows. Depending on whether the difference (l1 l1 ) is positive, zero, or negative, establish the direction of change of link l1 motion along the M-line from S to T positive, zero, or negative, respectively. Note

Additionally, for every reduction in the order of capacitance magnitude, the number of capacitors in that range should approximately double. In other words,

ij the mean for level j , summed over subscript i,

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i. =

if two 0.1-mF caps are used, four 0.01-mF caps should be used to achieve the same level of attenuation in the higher frequency band. The total number of caps, however, will be determined by the overall power requirements and the noise characteristics. To make things even easier, Xilinx has added a feature to their XPower tool that calculates the recommended decoupling capacitors based not only on the static characteristics of the FPGA device but also on the dynamic power usage. For an example design and vector set (not shown here), XPower calculates 7 mW of dynamic power in the core and determines the following decoupling strategy.

j overall mean of all ij ,

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Decoupling Network Summary: Cap Range (mF) #

Xijk average within a cell over its subjects scores,

X ij. average for the row i of A over related subjects scores, Xij. average for the column j of B over related subjects scores,

Capacitor Recommendations: Total for Vccint : 4 470.0 - 1000.0 : 1 0.0100 - 0.0470 : 1 0.0010 - 0.0047 : 2 -- Total for Vccaux : 8 470.0 - 1000.0 : 1 0.0470 - 0.2200 : 1 0.0100 - 0.0470 : 2 0.0010 - 0.0047 : 4 -- Total for Vcco25 : 8 470.0 - 1000.0 : 1 0.0470 - 0.2200 : 1 0.0100 - 0.0470 : 2 0.0010 - 0.0047 : 4

With this notation, if we only test for the main effect of factor B (similarly for the main effect of factor A), the null and alternative hypotheses can be written as

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The Main Sum Between, MSB , for J cells of factor B, is the average of estimated b variance of estimated column means (this ignoring factor A). That is, MSB = b nI J 1 (X j X)2

Minimally, a designer needs to put at least one capacitor near each power pin. Maximally, if high-frequency capacitors cannot t near the FPGA power pins, their effectiveness is greatly reduced and may need to be removed. This is discussed in the next section.

(7.12)